Junior Year (2025-2026) Independent Research Project | 300+ Hours
Optimize the circuit before it reaches the hardware.
QuantumLink is a quantum circuit optimizer built in Java. Its central idea is that many quantum circuits contain independent sub-problems: groups of qubits that never interact. Those groups can run in parallel on hardware rather than sequentially. QuantumLink automatically identifies those opportunities and then optimizes each piece for a target hardware architecture.
View the project on GitHubHow It Works
Normalize the circuit
Circuits are provided as JSON files. Before analysis, QuantumLink detects user-defined custom gates and expands them inline into their primitive components.
Find independent work
The circuit becomes a dependency graph, where gates are nodes and edges capture operations that share qubits and must occur in order. Connected-components analysis finds independent sub-circuits whose qubits never interact.
Route for the device
Each independent component is optimized against a target hardware topology, allowing separate chunks of computation to be executed in parallel rather than treating the circuit as one monolithic sequence.
Hardware-Aware Routing with SABRE
Each component passes through the SABRE algorithm, short for SWAP-Based Bidirectional Heuristic Search for Effective Qubit Mapping. SABRE maps logical qubits to physical qubits and inserts the minimum SWAP operations needed to meet a device's nearest-neighbor connectivity constraints.
It evaluates candidate SWAPs one layer ahead and makes multiple forward and backward passes to improve the initial mapping and reduce the total SWAP count.
Hardware Topologies
Mesh (Grid)
Qubits are arranged in a two-dimensional grid, with each connected to up to four neighbors. This mirrors processors such as Google's Sycamore and scales to 54 qubits.
Heavy-Hex
IBM's Eagle and Osprey processors use this layout, where each qubit connects to at most three neighbors. Lower connectivity trades routing flexibility for reduced error rates and scales to 127 qubits.
Both topology models share a common interface, making new hardware backends straightforward to add.
Tech Stack
- Java
- Core engine for circuit parsing, graph construction, connected-components analysis, SABRE routing, and hardware topology modeling.
- Python
- Circuit graph visualization with NetworkX and Matplotlib, plus quantum simulation and execution with Qiskit.
- JSON
- Circuit input and output format, compatible with the Quirk quantum circuit simulator.
What's Next
The partitioner and routing optimizer form the foundation of a broader transpilation pipeline. Planned additions include:
- Native gate-set reduction for specific hardware instruction sets
- A cost model that recommends the best topology for a circuit
- Support for superconducting, trapped-ion, neutral-atom, and photonic qubit modalities